1. Field of the Invention
The present invention relates to graphics processing systems. In particular, the present invention relates to the alignment of data signals with clock signals in a high speed graphics processing system.
2. Description of Related Art
A conventional graphics processing system includes a memory module, a memory interface unit (MIU) and a graphics controller. The memory module serves as a frame buffer for storing graphical data, which is displayed as a visual image on a monitor. The graphics controller updates this visual image by updating the graphics data stored within the memory module. The MIU is an interface, which controls the data transfer of the graphics data between the memory module and the graphics controller.
When the graphics controller is ready to manipulate the graphics data from the memory module, the MIU issues a read command signal for the memory module. The memory module responds to this command signal by transmitting the stored graphics data as a data signal to the graphics controller. When the graphics controller has completed manipulating this transmitted graphics data, the MIU issues a write command signal to the memory module for the memory module to receive a modified data signal, which replaces the original graphics data with the manipulated graphics data contained within the modified data signal. In an ideal system, each command signal and the corresponding response by the memory module occur within consecutive MIU clock (MCLK) cycles. Unfortunately, due to delays inherent within the system, misalignment within the graphics controller module between the MCLK signal and the data signals usually occurs.
To attempt to address this misalignment problem, recent graphics processing systems compensate for the inherent delay in the system by injecting the same latency, which exists in the data signal, into the MCLK signal. In particular, this conventional system relies upon modifying the MCLK signal, which is received by the graphics controller, by routing the MCLK signal through the memory module prior to being received by the graphics controller.
This reliance upon the returned MCLK signal, however, does not ensure a proper setup and hold time for the graphics controller to properly receive the data signal from the memory module. To more accurately align the setup and hold times of the MCLK signal with the data signal, conventional graphics processing systems utilize a programmable delay module in conjunction with a plurality of latches to inject an additional delay into the MCLK signal. In particular, by activating a number of stages of delay within the programmable delay module, the programmable delay module transforms the MCLK signal into a delayed MCLK (DCLK) signal. The plurality of latches, which are coupled to the programmable delay module, respond to receiving the DCLK signal by latching (sampling) the data signal, which is transmitted by the memory module. The graphics controller then retrieves this sampled data signal from the plurality of latches and manipulates the signal accordingly. When the DCLK signal contains a proper setup and hold time, the sampled data signal will match the transmitted data signal. However, if the stages of delay fail to adequately align the DCLK signal with the transmitted data signal, the sampled data signal will not match the transmitted data signal, thereby causing data corruption problems.
To determine the optimum number of stages of delay, which are needed for the programmable delay module to establish the necessary setup and hold times for the DCLK signal, manual trial and error is performed. Since manufacturing process variations between each component within the graphics processing system causes slightly different latency characteristics, this manual trial and error analysis must be repeated for each alternative component which is used in the system.
What is needed is a more efficient system and method for calibrating the graphics processing system with any circuit design through the automatic identification of the optimum number of stages of delay, which are needed to properly align the DCLK signal with the transmitted data signals.